Work / Fig 20 · 2024–
50–1000 nm American silicon
Dirt-cheap 50–1000 nm silicon on American soil — the missing layer under the PCB. A public argument that mature-node capacity is strategic infrastructure, not leftover from the 2 nm race. The lab notebook is the homemade semiconductor case.
A circuit board crowded with discrete parts sits beside a ceramic carrier holding a single die. One by one the board's parts lift off, shrink and settle into the die, and a block of its layout lights for each: a board collapsing into silicon. Then the parts return.
Mature-node thesis — the layer under the PCB
The constraint
America does not primarily need more 2 nm cathedrals. It needs dirt-cheap 50–1000 nm silicon at real scale, on American soil. Leading-edge wafers run tens of thousands of dollars; mask sets in the tens of millions; a production line in the tens of billions. That is why only a handful of companies can play at the frontier.
Mature nodes already represent most of global unit volume — power, analog, sensors, MCUs, automotive, industrial, RF, IoT. China understood that layer. The CHIPS Act aimed the money at the cathedral. The accessible foundation stayed thin.
What 50–1000 nm actually is
At the coarse end, a chip is a miniaturized PCB realized in silicon: interconnect, basic logic, local power, sensing front-ends, discrete-like blocks — at feature sizes where the physics is still gentle. The opportunity is not the last nanometer of gate length. It is collapsing expensive, failure-prone boards into affordable, reliable, highly integrated silicon that does not require trillion-dollar infrastructure.
Lithography at these sizes does not need EUV. Maskless UV, DLP, and related tools already reach the necessary resolution. Independent experimenters — including this lab — are showing functional devices at these scales without a multi-billion-dollar toolset.
This lab
The hands-on half lives on the homemade semiconductor case: a 4" wafer, maskless mSLA, and a ~100 μm calibration pattern, in progress. Status: research. The public write-up stops at the goal and the scale. No protocols, no chemistry, no how-to.
The same person who patented an SSTO architecture is arguing, in public, that coarse American silicon is how hardware startups, edge AI, and wartime capacity actually scale.